1. Field of the Invention
The present invention relates to a digital filter device, and in particular to a digital filter device for filtering a plurality of signals with a single digital filter.
With an advanced digital signal processing technology in recent years, a digital filter is indispensable for general fields of technology such as communications and controls. It is possible to filter a plurality of signals (data strings) with a single digital filter commonized, i.e. made in common. This filtering is required corresponding to a characteristic of a signal to be processed.
2. Description of the Related Art
FIG. 7 shows a signal processing circuit (digital filter) 90 disclosed in Japanese Patent Application Laid-open No.11-220355 as a prior art example (1). This signal processing circuit 90 comprises a signal time-division multiplexer 91 for time-division multiplexing a plurality of digital signals (input signal 803, re-input signal 805), and a multiplexing filter portion 92 for performing plural kinds of filterings commonized within a sampling period for the above time-division multiplexing.
Furthermore, the signal processing circuit 90 comprises a signal detector 93 which detects and temporarily holds the re-input signal 805 from an output signal 807 of the multiplexing filter portion 92 with a timing of the above time-division multiplexing, and feeds it back to the signal time-division multiplexer 91 to be used for the next filtering. This signal detector 93 provides a desired final output signal 808.
Furthermore, the signal processing circuit 90 comprises a timing generator 94 which inputs a clock 804 to provide a timing pulse 806 to the multiplexing filter portion 92 and the signal detector 93.
Namely, by the signal detector 93 feeding back the re-input signal 805 obtained by filtering the input signal 803 to the signal time-division multiplexer 91, the multiplexing filter portion 92 can perform plural kinds of filterings commonized with respect to the input signal 803 within one sampling period.
FIG. 8 shows a digital filter 80 disclosed in Japanese Patent Application Laid-open No.63-141406 as a prior art example (2). This digital filter 80 performs a time-division multiplexed filtering with latch circuits 81_1, 81_2 which input and time-divide a plurality of input data strings (two input signals 800_1, 800_2 in FIG. 8) to reduce the data width to one of the time-divided number to be outputted, and delay circuits 83_1-83_4 which delay latch outputs (3 state output in FIG. 8) of the latch circuits 81_1, 81_2 by a time width of a sample clock corresponding to the above-reduced data width.
Namely, the input signals 800_1, 800_2 respectively latched by the latch circuits 81_1, 81_2 are inputted to the delay circuit 83_1 by turns in the form of the input signal 801 via a wired OR circuit 82, and thereafter sequentially delayed by a time width of a sample clock to be shifted to the delay circuits 83_2-83_4.
Accordingly, the output signals of the wired OR circuit 82 and the delay circuits 83_2, 83_4 at a timing of a certain sample clock are respectively, for example, the input signal 800_1, the input signal 800_1 delayed by 2 sample clocks, and the input signal 800_1 delayed by 4 sample clocks. With these signals, computers 84_1, 84_2 perform filtering. The latch circuit 85_1 latches the computation 802 of the computer 84_2.
Similarly, at the next sample clock timing, the filtering operation of the input signal 800_2 is computed, the result of which is latched by the latch circuit 85_2.
A prior art example (3) in which the digital filter 80 shown in FIG. 8 is applied to controls of MEMS (Micro Electro Mechanical System) optical switch will now be described referring to FIGS. 9-11.
FIG. 9 shows a configuration example of a general 64 ch×64 ch MEMS optical switch. This MEMS optical switch is composed of a collimator array 140 arranged on the input side consisting of the collimators 141_1-141_64, a mirror array 130 arranged on the input side consisting of mirrors 131_1-131_64 (hereinafter, occasionally represented by a reference 131), a mirror array 150 arranged on the output side consisting of mirrors 151_1-151-64 (hereinafter, occasionally represented by a reference 151), and a collimator array 160 arranged on the output side consisting of collimators 161_1-161_64.
The collimators 141_1-141_64 and the mirrors 131_1-131_64 respectively correspond to input channels ch1-ch64, and the mirrors 151_1-151_64 and the collimators 161_1-161_64 respectively correspond to output channels ch1-ch64.
FIG. 10 shows an arrangement of mirror control electrodes in a general MEMS optical switch, and particularly electrodes of the input side mirror 131_1 and the output side mirror 151_8. The electrodes of the input side mirror 131_1 are composed of electrodes x1(−), x1(+), and electrodes y1(−), y1(+), and the electrodes of the output side mirror 151_8 are composed of electrodes x2(−), x2(+), and electrodes y2(−), y2(+).
The case where an optical signal of the input channel ch1 is switched to the output channel ch8 will now be described.
An optical signal 700a from the collimator 141_1 of the input channel ch1 irradiates the input side mirror 131_1. The electrode x1(+) of the input side mirror 131_1 is applied with a voltage to tilt the mirror 131_1 by an electrostatic effect, whereby an optical signal 700b reflected by the mirror 131_1 is irradiated to the mirror 151_8 of the output channel ch8.
Also, the electrode x2(+) of the mirror 151_8 is applied with a voltage, whereby an optical signal 700c reflected by the mirror 151_8 is irradiated to the collimator 161_8 of the output channel ch8. At this moment, without radiations of the optical signal 700c perpendicular onto the collimator 161_8, the optical loss will be increased.
When the optical signal of the input channel ch1 is switched to the output channel ch64, in FIG. 9, the electrodes x1(+) and y1(−) of the input side mirror 131_1 are applied with voltages, an optical signal 700d reflected by the mirror 131_1 is irradiated onto the mirror 151_64 of the output channel ch64.
Moreover, the electrodes x3(+) and y3(−) (not shown) of the mirror 151_64 are applied with voltages, whereby an optical signal 700e reflected by the mirror 151_64 is irradiated onto the collimator 161_64 of the output channel ch64.
Thus, switching over the optical routes by controlling the mirror angles, the MEMS optical switch requires no conversion from optical signals to electrical signals, has no dependencies on wavelength and polarization, and is small-sized. To this end, the MEMS optical switch receives attention as an exceeded switch in the application thereof to WDM (Wavelength Division Muliplex) network.
However, the mirrors 131, 151 have a transient characteristic such as resonance due to mechanical characteristics. This transient characteristic causes an increased switchover time of the MEMS optical switch.
FIG. 11 shows a MEMS optical switch control circuit, as a prior art example (3), using a digital filter for minimizing the above-noted switchover time.
This control circuit is composed of an open control portion for designating the angles of the mirrors 131, 151 and a feedback control portion for feeding back the control result to the open control portion.
The open control portion comprises computing processors 10z_1-10z_64 (hereinafter, occasionally represented by a reference 10z) for generating the digital data (four data: data of 256 (=64×4) in total), corresponding to the channels ch1-ch64) for controlling the mirrors 131, 151 respectively, latch circuits 81z_1-81z_64 (hereinafter, occasionally represented by a reference 81z) for latching those data, a selector 87z for outputting a digital filter input signal 801z obtained by sequentially selecting, on a time-division basis, the data latched by the latch circuits 81z_1-81z_64, a digital filter 80z for generating an output signal 802z obtained by filtering, on a time-division basis, the input signal 801z, and latch circuits 85z_1-85z_64 for sequentially latching, on a time-division basis, the output signal 802z. 
The digital filter 80z is different in configuration from the digital filter 80 shown in FIG. 8, but both are basically the same in operation in that the former comprises the delay circuits 88_1-88_256 and 89_1-89_256 corresponding to 256 data (channel number “64”× control number “4”) latched by the latch circuit 81z. 
Namely, for example, one of four data latched by the latch circuit 81z−1 is added at an adder 31_1, and then shifted to the delay circuits 88_1-88_256 and 89_1-89_256 by the clock. At the shift timings to the delay circuits 88_256, 89_256, the filter output signal 802z filtered corresponding to the data of the latch circuit 81z_1 is outputted from an adder 31_3 to be latched by the latch circuit 85z_1.
Similarly, the data obtained by filtering the data of the latch circuits 81z_2-81z_64 are respectively latched by the latch circuits 85z_2-85z_64.
The control circuit further comprises DA converters 50_1-50_64 (hereinafter, occasionally represented by a reference 50) for converting into analog signals respectively the data latched by the latch circuits 85z_1-85z_64, and drivers 110_1, . . . , 110_64, 111_1, . . . , 111_64 (hereinafter, occasionally represented by references 110, 111) for driving the mirrors 131, 151 based on the converted analog output signal 708.
In operation, the computing processor 10z computes data for driving the mirrors 131, 151. The data are filtered, on a time-division basis, by the digital filter 80z. This digital filter 80z is set to have the minimum operation time of the mirrors 131, 151, that is the minimum switchover time of the optical switch. The filtered data are converted into an analog signal by the DA converter 50 and is provided to the drivers 110, 111, which drive the mirrors 131, 151.
The feedback control portion is composed of optical level detectors 170_1-170_64 (hereinafter, occasionally represented by a reference 170) for detecting the levels of the optical signals 700_1 (ch1)-700_64 (ch64) of the output channels ch1-ch64 respectively, and AD converters 180_1-180_64 for converting the detected optical level into digital data to be provided to the computing processors 10z_1-10z_64.
In operation, the optical level signal 701 of the output channels ch1-ch64 respectively detected by the optical level detector 170 are provided to the computing processor 10z as a digital signal 702 (702_1-702_64) converted from the analog signal.
Namely, the operated angle data of the mirrors 131, 151 are fed back to the computing processor 10z. The computing processor 10z corrects the input signal (mirror control data) 800_1-800_64 so that deviations of the optical signal 700_1-700_64 caused by mechanical and electrical errors of the mirror may be amended.
If various digital filters as above-noted are provided respectively for input data from several hundreds of channels, the required hardware is quite large-sized, resulting in a disadvantageous cost, consumption power, and mounting area.
This enlarges the circuit size of the multiplier, adder, and delay circuits required for filtering as the bit width of the input data increases, resulting in much more disadvantages.
Furthermore, it is said to be impossible to provide digital filters respectively for input data from 1000 and more channels. Therefore, it becomes necessary to commonize the above-noted digital filters, with time-division multiplexing.
However, the prior art signal processing circuit (digital filter) shown in FIG. 7 is suitable for the filtering upon a completed processing within one sampling period, while it is not suitable for the filtering upon uncompleted processing within one sampling period.
Namely, since the delay circuit (not shown) included in the multiplexing filter portion 92 of the signal processing circuit has no residual data necessary for the next filtering when the processing is uncompleted within one sampling period, no continuity can be kept for the output data strings as filtered.
Also, the digital filter shown in FIG. 8 and the digital filter employed in FIG. 11 require internal delay circuits and latch circuits on the input side respectively by the number of input channels. Therefore, this type of digital filter assumes a large-sized circuit for the filtering over e.g. 1000 channels, resulting in inadequate usages.
This type of digital filter also requires to make a unit time delay by the delay circuit with the same timing as the time-division processing, so that it can not perform the filtering for e.g. time-divided data fluctuating in periodicity such as data collected from IP networks, or data with the sequence or order of plural channels time-divided being exchanged.
Furthermore, this type of digital filter can not set the filter coefficient for each mirror to provide an optimum response characteristic for each mirror when the characteristics of the mirrors are different from each other.